A 0.6 V Fast-Transient-Response 180 nm CMOS Digital LDO with Coarse-Fine Tuning and Analog Enhancement

A coarse-fine tuning technique with analog enhancement (AE) operation is proposed for the digital low-dropout (DLDO) regulator. Once the undershoot or overshoot is detected, the coarse tuning quickly finds out the coarse control loop in which the load current should be located, with large power PMOS size and high sampling frequency. Then, the fine tuning, with reduced power PMOS size and sampling frequency, regulates the DLDO to the desired output voltage and takes over the steady-state operation for high accuracy and current efficiency. By using time-domain comparator instead of voltage-domain comparator, the voltage signal is converted to time signal and the comparison result is obtained through phase discriminator to identify phase difference, so that DLDO can realize low-voltage operation. Meanwhile, the AE operation is introduced to reduce the overshoot/undershoot voltage by increasing the transient current of the power PMOS. The proposed DLDO is designed using a 180 nm 1P6M CMOS process with a 0.09 mm(2) active area. The post-simulated undershoot and overshoot voltages are only 50.26 and 34.66 mV, respectively, when the load current changes between 1 and 2.5 mA, and the maximum recovery time is 305.3 ns.

Automated summary

This paper proposes a coarse-fine tuning technique for DLDO regulators, along with the use of analog enhancement (AE) operation to reduce overshoot/undershoot voltage and enable low-voltage operation.