4.6 Article

A 125 KHz, Single-Stage, Dual-Output Wireless Power Receiver with PSM Modulation

Journal

ELECTRONICS
Volume 11, Issue 8, Pages -

Publisher

MDPI
DOI: 10.3390/electronics11081184

Keywords

power conversion efficiency; regulating rectifier; wireless power transfer

Funding

  1. peers at the Institute of Microelectronics of the Chinese Academy of Sciences - National Key R&D Program of China [2019YFB2204900]

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This paper presents a 125 KHz single-stage dual-output wireless power receiver using pulse skip modulation. The receiver eliminates interstage loss, improves power conversion efficiency, and reduces chip area and cost by only using one stage and four power transistors without an inductor.
This paper presents a 125 KHz, single-stage, dual-output wireless power receiver with pulse skip modulation (PSM). Multi-output receivers are proposed to supply different modules in one system. Conventional multi-output receivers contain a rectifier and a multi-output regulator, which degrade the power conversion efficiency (PCE) due to interstage loss of the rectifier and the regulator. Additionally, existing single-inductor multi-output (SIMO) receivers exhibit a cross-regulation phenomenon because of the sharing inductor, which decreases the stability of the output voltages, and the use of an inductor in SIMO receivers increases the cost of the circuit. The proposed receiver in this article realizes rectification and regulation in only one stage, which eliminates interstage loss; this improves the power conversion efficiency of the system and realizes dual-output voltages with only four power transistors without an inductor, which reduces the chip area and minimizes cost. There is no cross-regulation in this dual-output architecture because the dual-output voltages are charged by different phases of the input signal. PSM modulation was adopted to regulate output voltages for higher efficiency. The proposed single-stage, dual-output regulating rectifier delivers a maximum power of 47 mW, and the dual-output voltages are 1.8 V and 2 V. This receiver is designed by a 0.18 mu m complementary metal-oxide-semiconductor (CMOS) process and realizes a peak efficiency of 86% when the output power ranges from 15 mW to 47 mW.

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