4.6 Article

A 1.8 V Low-Power Low-Noise High Tunable Gain TIA for CMOS Integrated Optoelectronic Biomedical Applications

Journal

ELECTRONICS
Volume 11, Issue 8, Pages -

Publisher

MDPI
DOI: 10.3390/electronics11081271

Keywords

low-voltage; low-power; low-noise; tunable gain; CMOS Integrated Technology; optoelectronics; transimpedance amplifier (TIA); biomedical applications

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This paper presents a novel solution for a transimpedance amplifier (TIA) in biomedical applications. The proposed solution operates with nanoampere input pulsed currents and has been analyzed for its performance through accurate post-layout simulations.
This paper reports on a novel solution for a transimpedance amplifier (TIA) specifically designed as an analog conditioning circuit for low-voltage, low-power, wearable, portable and implantable optoelectronic integrated sensor systems in biomedical applications. The growing use of sensors in all fields of industry, biomedicine, agriculture, environment analysis, workplace security and safety, needs the development of small sensors with a reduced number of electronic components to be easily integrated in the standard CMOS technology. Especially in biomedicine applications, reduced size sensor systems with small power consumption are of paramount importance to make them non-invasive, comfortable tools for patients to be continuously monitored even with personalized therapeutics and/or that can find autonomous level of life using prosthetics. The proposed new TIA architecture has been designed at transistor level in TSMC 0.18 mu m standard CMOS technology with the aim to operate with nanoampere input pulsed currents that can be generated, for example, by Si photodiodes in optical sensor systems. The designed solution operates at 1.8 V single supply voltage with a maximum power consumption of about 36.1 mu W and provides a high variable gain up to about 124 dB Omega (with fine- and coarse-tuning capabilities) showing wide bandwidth up to about 1.15 MHz and low-noise characteristics with a minimum noise floor level down to about 0.39 pA/ root Hz. The overall circuit is described in detail, and its main characteristics and performances have been analyzed by performing accurate post-layout simulations.

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