Surface loss calculations and design of a superconducting transmon qubit with tapered wiring

Analytical formulas are presented for simplified but useful qubit geometries that predict surface dielectric loss when its thickness is much less than the metal thickness, the limiting case needed for real devices. These formulas can thus be used to precisely predict loss and optimize the qubit layout. Surprisingly, a significant fraction of surface loss comes from the small wire that connects the Josephson junction to the qubit capacitor. Tapering this wire is shown to significantly lower its loss. Also predicted are the size and density of the two-level state (TLS) spectrum from individual surface dissipation sites.

Automated summary

Analytical formulas are presented for simplified qubit geometries that can predict surface dielectric loss and optimize qubit layout. The study reveals that a large part of surface loss comes from the small wire connecting the Josephson junction and the qubit capacitor. The size and density of the two-level state (TLS) spectrum from individual surface dissipation sites are also predicted.