4.7 Article

A 13-Level Switched-Capacitor Multilevel Inverter With Single DC Source

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JESTPE.2021.3077604

Keywords

Capacitors; Topology; Switches; Stress; Discharges (electric); Boosting; Power system measurements; Maximum blocking voltage (MBV); multilevel inverters (MLIs); single source; switched capacitor (SC)

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This article proposes a novel 13-level inverter single source, switched-capacitor multilevel inverter (SSC-MLI) structure, which is suitable for renewable energy applications with lower input voltage source magnitude. The advantages of this structure include high-power density and high efficiency, as it eliminates forward conduction loss and reverse recovery delay by not using diodes.
In this article, a novel 13-level inverter single source, switched-capacitor multilevel inverter (SSC-MLI) is proposed. This topology is suitable for renewable energy applications using less input voltage source magnitude. This structure is capable of boosting the input voltage six times with the help of switched capacitors. The capacitors are automatically balanced without any control algorithms, complex circuits, or closed-loop controllers. The advantages of the proposed structure are high-power density and high efficiency by the use of only switches. Since, there are no diodes there is no forward conduction loss, and no reverse recovery delay. The maximum blocking voltage across the individual switch is three times the input voltage. The functionality of the SSC-MLI is described in detail. The capacitance calculation and optimum value of capacitors are discussed. A suitable comparison is presented for the proposed structure with the existing literature to check the inverter performance. The power loss for exiting a 13-level inverter is presented. The simulation is carried out for both pure resistive and inductive load. Later, the experimental results are presented for variation in frequency, dynamic change in load, variation in modulation index, and step-change in input voltage to validate the proposed topology performance and feasibility.

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