Journal
2D MATERIALS
Volume 9, Issue 2, Pages -Publisher
IOP Publishing Ltd
DOI: 10.1088/2053-1583/ac5b17
Keywords
dichalcogenide semiconductor; indium selenide; ferroelectric semiconductor field effect transistor (FeSFET); low-temperature processing; temperature-dependent transport; memory performance
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Funding
- National Science Foundation (NSF) [1433378, DMR-1539916]
- center for 3D Ferroelectric Microelectronics (3DFeM), an Energy Frontier Research Center - U.S. Department of Energy (DOE), Office of Science, Basic Energy Sciences [DE-SC0021118]
- U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences Energy Frontier Research Centers program [DE-SC0020145]
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This study demonstrates low-temperature processed transistors compatible with the back-end-of-the-line, which provides a new approach for improving energy efficiency and chip performance.
As scaling becomes increasingly difficult, there is growing interest in vertical or three-dimensional stacking of transistors and especially memory. Ferroelectric semiconductor field effect transistors can be key enablers to improve energy efficiency and overall chip and memory performance. In this work, low-temperature processed, back-end-of-the-line compatible transistors were demonstrated by depositing a layered chalcogenide ferroelectric semiconductor, beta-phase In2Se3, at temperature as low as 400 degrees C. Top gate n-channel In2Se3 thin film transistors were fabricated with field-effect mobility similar to 1 cm(2) V-1 s(-1), and simple polarization switching based memory results are presented.
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