Low-Temperature (≤500 °C) Complementary Schottky Source/Drain FinFETs for 3D Sequential Integration

In this work, low-temperature Schottky source/drain (S/D) MOSFETs are investigated as the top-tier devices for 3D sequential integration. Complementary Schottky S/D FinFETs are successfully fabricated with a maximum processing temperature of 500 degrees C. Through source/drain extension (SDE) engineering, competitive driving capability and switching properties are achieved in comparison to the conventional devices fabricated with a standard high-temperature (>= 1000 degrees C) process flow. Schottky S/D PMOS exhibits an ON-state current (I-ON) of 76.07 mu A/mu m and ON-state to OFF-state current ratio (I-ON/I-OFF) of 7 x 10(5), and those for NMOS are 48.57 mu A/mu m and 1 x 10(6). The CMOS inverter shows a voltage gain of 18V/V, a noise margin for high (NMH) of 0.17 V and for low (NML) of 0.43 V, with power consumption less than 0.9 mu W at V-DD of 0.8 V. Full functionality of CMOS ring oscillators (RO) are further demonstrated.

Automated summary

This work investigates low-temperature Schottky source/drain (S/D) MOSFETs as the top-tier devices for 3D sequential integration. The study successfully fabricates complementary Schottky S/D FinFETs with a maximum processing temperature of 500 degrees C. Through source/drain extension engineering, the devices achieve competitive driving capability and switching properties compared to conventional devices. The experimental results demonstrate the excellent performance of the devices in CMOS inverters and ring oscillators.