N-Type Nanosheet FETs without Ground Plane Region for Process Simplification

This paper proposes a simplified fabrication processing for nanosheet Field-Effect Transistors (FETs) part of beyond-3-nm node technology. Formation of the ground plane (GP) region can be replaced by an epitaxial grown doped ultra-thin (DUT) layer on the starting wafer prior to Si-x/SiGe1-x stack formation. The proposed process flow can be performed in-situ, and does not require changing chambers or a high temperature annealing process. In short, conventional processes such as ion implantation and subsequent thermal annealing, which have been utilized for the GP region, can be replaced without degrading device performance.

Automated summary

This paper proposes a simplified fabrication process for nanosheet Field-Effect Transistors (FETs) in beyond-3-nm node technology, by replacing the formation of the ground plane (GP) region with an epitaxial grown doped ultra-thin (DUT) layer. The proposed process flow can be performed in-situ, without the need for equipment change or high temperature annealing, and it does not degrade device performance.