Journal
IEEE TRANSACTIONS ON SYSTEMS MAN CYBERNETICS-SYSTEMS
Volume 52, Issue 3, Pages 1901-1915Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TSMC.2020.3035612
Keywords
Synapses; Memristors; Resistance; Threshold voltage; Training; Task analysis; Intelligent control; Hierarchical temporal memory (HTM); memristor; neural networks; neuromorphic architecture; spatial pooler (SP)
Funding
- National Key Research and Development Program of China [2016YFB0800402]
- Innovation Group Project of the National Natural Science Foundation of China [61821003]
- National Natural Science Foundation of China [61673188, 61761130081]
- Foundation for Innovative Research Groups of Hubei Province of China [2017CFA005]
- 111 Project on Computational Intelligence and Intelligent Control [B18024]
- Missouri University of Science and Technology Mary K. Finley Endowment
- Missouri University of Science and Technology Intelligent Systems Center
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This article investigates the hardware implementation of hierarchical temporal memory (HTM), a brain-inspired machine learning algorithm that mimics the functions of the neocortex. A memristor-based SP (MSP) circuit structure is designed to accelerate the execution of the algorithm. Simulation results validate the effectiveness of MSP.
This article investigates hardware implementation of hierarchical temporal memory (HTM), a brain-inspired machine learning algorithm that mimics the key functions of the neocortex and is applicable to many machine learning tasks. Spatial pooler (SP) is one of the main parts of HTM, designed to learn the spatial information and obtain the sparse distributed representations (SDRs) of input patterns. The other part is temporal memory (TM) which aims to learn the temporal information of inputs. The memristor, which is an appropriate synapse emulator for neuromorphic systems, can be used as the synapse in SP and TM circuits. In this article, a memristor-based SP (MSP) circuit structure is designed to accelerate the execution of the SP algorithm. The presented MSP has properties of modeling both the synaptic permanence and the synaptic connection state within a single synapse, and on-device and parallel learning. Simulation results of statistic metrics and classification tasks on several real-world datasets substantiate the validity of MSP.
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