FinFET-Based Inverter Design and Optimization at 7 Nm Technology Node

Stress engineering is one of the best techniques to enhance the potential of a device. In the first phase of this work, the impact of stress on the physical and electrical performance of FinFET based inverter is investigated using 2D and 1D stress mapping techniques. Electrons and holes mobility enhancements are presented in the sidewall fins of and < 110> direction respectively, by resulting tensile stress in n-FinFET and compressive stress in p-FinFET. According to the sidewall orientation ( or < 110>), the amount of mobility enhancement of both the electrons and holes are resulting in more than 100% (>100%) and less than 25% (<25%) respectively. In the second phase, Design Technique Co-Optimization (DTCO) method is approached in inverter standard cells generation to enable the VLSI digital system design flow based on standard cells using FinFET. FinFET-based inverters at 7 nm technology nodes is designed using the GTS TCAD framework. The optimal electrical characteristics such as current density, throughput delay, average power dissipation, and switching energy are presented with optimal design.

Automated summary

Stress engineering is a powerful technique to improve device performance. This study investigates the impact of stress on the physical and electrical performance of FinFET-based inverters. The results show enhanced electron and hole mobility in the sidewall fins, resulting in improved device performance. The study also demonstrates the use of Design Technique Co-Optimization (DTCO) method to generate standard cells for VLSI digital system design using FinFET technology, with optimized electrical characteristics.