4.7 Article

A Neuromorphic CMOS Circuit With Self-Repairing Capability

Journal

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNNLS.2020.3045019

Keywords

Synapses; Neurons; Calcium; Biological system modeling; Mathematical model; Neuromorphics; Integrated circuit modeling; Astrocyte; CMOS implementation; neuromorphic circuit; self-repairing mechanism; tripartite synapse

Funding

  1. Spanish Grant from the Ministry of Science and Innovation (European Regional Development Fund) [PID2019-105556GB-C31]
  2. Kermanshah University of Medical Sciences, Kermanshah, Iran

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Neurophysiological observations show that the brain can detect and repair impaired synapses, especially through the collaboration of astrocytes retrograde signaling with nearby neurons. A CMOS neuromorphic circuit with self-repairing capabilities has been proposed based on these findings, which can compensate for damaged synapses by modifying signals of healthy synapses. This fault-tolerant circuit is considered a key candidate for future silicon neuronal systems and neuro-inspired circuits.
Neurophysiological observations confirm that the brain not only is able to detect the impaired synapses (in brain damage) but also it is relatively capable of repairing faulty synapses. It has been shown that retrograde signaling by astrocytes leads to the modulation of synaptic transmission and thus bidirectional collaboration of astrocyte with nearby neurons is an important aspect of self-repairing mechanism. Specifically, the retrograde signaling via astrocyte can increase the transmission probability of the healthy synapses linked to the neuron. Motivated by these findings, in the present research, a CMOS neuromorphic circuit with self-repairing capabilities is proposed based on astrocyte signaling. In this way, the computational model of self-repairing process is hired as a basis for designing a novel analog integrated circuit in the 180-nm CMOS technology. It is illustrated that the proposed analog circuit is able to successfully recompense the damaged synapses by appropriately modifying the voltage signals of the remaining healthy synapses in the wide range of frequency. The proposed circuit occupies 7500-mu m(2) silicon area and its power consumption is about 65.4 mu W. This neuromorphic fault-tolerant circuit can be considered as a key candidate for future silicon neuronal systems and implementation of neurorobotic and neuro-inspired circuits.

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