Vertical MoS2 transistors with sub-1-nm gate lengths

Ultra-scaled transistors are of interest in the development of next-generation electronic devices(1-3). Although atomically thin molybdenum disulfide (MoS2) transistors have been reported(4), the fabrication of devices with gate lengths below 1 nm has been challenging(5). Here we demonstrate side-wall MoS2 transistors with an atomically thin channel and a physical gate length of sub-1 nm using the edge of a graphene layer as the gate electrode. The approach uses large-area graphene and MoS2 films grown by chemical vapour deposition for the fabrication of side-wall transistors on a 2-inch wafer. These devices have On/Off ratios up to 1.02 x 10(5) and subthreshold swing values down to 117 mV dec(-1). Simulation results indicate that the MoS2 side-wall effective channel length approaches 0.34 nm in the On state and 4.54 nm in the Off state. This work can promote Moore's law of the scaling down of transistors for next-generation electronics.

Automated summary

In this study, sidewall MoS2 transistors with sub-1 nm physical gate length were successfully fabricated by using the edge of a graphene layer as the gate electrode. These devices exhibit excellent performance characteristics and could potentially advance the scaling down of next-generation electronic devices.