An Architectural-Level Reliability Improvement Scheme in STT-MRAM Main Memory

DRAM technologies in main memory of computer systems face fundamental scalability challenges beyond 10 nm node. In recent years, Spin-Transfer Torque Magnetic Random Accesses Memory (STT-MRAM) has attracted much attention as an alternative to DRAM in main memory. Storing data as a resistance state instead of an electric charge solves the issues with DRAMs. Non-volatility, near-zero static power dissipation, high speed, and high endurance are some of the advantages of SIT-MRAMs. However, STT-MRAMs suffer from problems with write and retention failures due to their stochastic nature. The data retention failure probability at the main memory level is high due to long data idle times because of the multiple cache levels and long distance from the processor registers. In addition, if the write failure occurs in one bit, the entire data block is erroneous, so the write failure cannot be ignored as well. This study improves the reliability of main memory at two levels of memory with the minimum change in the architecture. At the first level, the data block is prepared before writing to memory, and the main cause of write failure, which is the 0 -> 1 transitions, is completely eliminated. In the second level, the data blocks returned to main memory are managed to mitigate the data retention failure and to reduce the idle time intervals of data blocks. The simulation results show that the proposed scheme reduces the write failure probability by 95.8% and the data retention failure by 33.6%. The side-effect of these reductions is imposing only 1.5% energy consumption overhead and 1.2% performance degradation on the system.

Automated summary

This study improves the reliability of computer system main memory with minimal changes in architecture, reducing the probability of write and retention failures.