Bias-stress instabilities in low-temperature thin-film transistors made of Al2O3 and ZnO films deposited by PEALD

Thin film transistors (TFT) were fabricated by plasma-enhanced atomic layer deposition (PE-ALD) of aluminum oxide ( Al2O3) and zinc oxide (ZnO) on glass substrates at 70 degrees C. The thicknesses of the Al2O3 (gate dielectric) and ZnO (n-type semiconductor) were 25 and 60 nm, respectively. Prior to Al2O3 deposition Cr/Au gate contacts were patterned using photolithography. Photolithography was also used to define aluminum source and drain contacts with thickness of 200 nm. The W/L ratio of the fabricated transistors was varied between 1 and 8 by varying the channel length L (40, 20 10 and 5 jm), while the channel width W was kept constant to 40 jm. Capacitance-voltage measurements revealed good uniformity of the Al2O3 layer with a dielectric constant value of similar to 8. The sheet resistance of the ZnO layer was found to be similar to 2400 Omega/sq. The TFT electrical characterization showed that the saturation mobility does not depend substantially on W/L ratio and had values between 0.82 and 1.1 cm(2)/V-s, while the subthreshold slope varied between 190 and 207 mV/dec. Moreover, a high on/off current ratio of similar to 10(7) was determined. The threshold voltage (V-th) instability was also characterized by positive and negative bias stress leading to a Vth shift of about -0.3 V and -0.8 V, respectively.

Automated summary

Thin film transistors (TFT) were fabricated using plasma-enhanced atomic layer deposition (PE-ALD) technique at 70 degrees C on glass substrates. The fabricated transistors showed good electrical characteristics.