Optimized partitioning and priority assignment of real-time applications on heterogeneous platforms with hardware acceleration

Hardware accelerators, such as those based on GPUs and FPGAs, offer an excellent opportunity to efficiently parallelize functionalities. Recently, modern embedded platforms started being equipped with such accelerators, resulting in a compelling choice for emerging, highly computational intensive workloads, like those required by next-generation autonomous driving systems. Alongside the need for computational efficiency, such workloads are commonly characterized by real-time requirements, which need to be satisfied to guarantee the safe and correct behavior of the system. To this end, this paper proposes a holistic framework to help designers partition real-time applications on heterogeneous platforms with hardware accelerators. The proposed model is inspired by a realistic setup of an advanced driving assistance system presented in the WATERS 2019 Challenge by Bosch, further generalized to encompass a broader range of heterogeneous architectures. The resulting analysis is linearized and used to encode an optimization problem that jointly (i) guarantees timing constraints, (ii) finds a suitable task-to-core mapping, (iii) assigns a priority to each task, and (iv) selects which computations to accelerate, seeking for the most convenient trade-off between the smaller worst-case execution time provided by accelerators and synchronization and queuing delays.

Automated summary

This paper proposes a holistic framework for partitioning real-time applications on heterogeneous platforms with hardware accelerators. The model is inspired by a realistic setup of an advanced driving assistance system and can be applied to a broader range of heterogeneous architectures. The resulting analysis solves timing constraints, task-to-core mapping, task prioritization, and selection of computations to accelerate to find the most suitable trade-off between the smaller worst-case execution time provided by accelerators and synchronization and queuing delays.