Data block manipulation for error rate reduction in STT-MRAM based main memory

Downscaling of semiconductor technology has led DRAM-based main memories to lag behind emerging non-volatile memories, e.g., Spin-Transfer Torque Magnetic Random-Accesses Memory (STT-MRAM). Although using STT-MRAMs reduces the issues with technology scaling, the common read/write path and stochastic switching lead to write failure (WF) and read disturbance (RD), which degrades their reliability. In STT-MRAMs, 0 -> 1 transitions are the predominant cause of WF, and RD is associated only with cells storing 1. This paper proposes a low-cost microarchitectural technique to mitigate WF and RD in STT-MRAMs. By eliminating 0 -> 1 transitions in write operations via prewriting the blocks and using an effective encoding to reduce the number of 1s in read operations, we improve the reliability. The simulation results show an increase in mean time to WF by 3230% and reduction in RD rate by 22%. Reliability is enhanced by imposing only 0.1%, 1.52%, and 1.19% area, power consumption, performance overheads, respectively.

Automated summary

This paper proposes a low-cost microarchitectural technique to mitigate write failure and read disturbance in Spin-Transfer Torque Magnetic Random-Accesses Memory (STT-MRAM). By prewriting the blocks and using effective encoding, the reliability of STT-MRAM is improved.