A radiation tolerant clock generator for the CMS endcap timing layer readout chip

We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named 1jCDR from the Low Power Gigabit Ransceiver (IpGBT) project. The 1jCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear Energy Transfer (LET) from 1.3 to 62.5 MeV x cm(2)/mg.

Automated summary

This article presents the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). The chip is based on an improved version of the 1jCDR clock synthesis circuit and features an automatic frequency calibration (AFC) module. It has undergone extensive testing, including Total Ionizing Dose (TID) testing and Single Event Upset (SEU) testing with heavy ions.