Double Differential Blocks Based Frequency Compensation: A Four-Stage CMOS Amplifier

In this paper, an efficient frequency compensation method is investigated for a four-stage CMOS amplifier. The frequency compensation network includes two sets of capacitors at the differential block output. The proposed compensated amplifier is described symbolically to obtain the transfer function. Meanwhile, the proposed configuration is designed at the circuit level and is simulated via 0.18 mu m CMOS technology. Compared to the other existing methods, the proposed amplifier satisfies the figure of merits considerably. This stems from the fact that lower capacitor values are used to perform compensation, leading to lower die occupation, and reach boosted gain bandwidth products. Leveraging both the configuration and design procedure, a high-performance four-stage is presented in this paper.

Automated summary

An efficient frequency compensation method for a four-stage CMOS amplifier is investigated in this paper. The proposed compensation method, which uses lower capacitor values, leads to reduced die occupation and improved gain bandwidth products.