Journal
JOURNAL OF ALLOYS AND COMPOUNDS
Volume 898, Issue -, Pages -Publisher
ELSEVIER SCIENCE SA
DOI: 10.1016/j.jallcom.2021.162918
Keywords
Copper oxide; Silicon oxide; Resistive switching; Annealing; Interfacial layer
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Funding
- Ministry of Science and Technology of Taiwan, ROC
- MOST [107-2221-E224-031-MY3]
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This paper investigates the effects of a SiOx interfacial layer on Ag/CuxO/SiOx/n+-Si write-once-read-many-times (WORM) memories. The results show that annealed CuxO devices exhibit improved ON/OFF current ratios, endurance characteristics, and read-disturb immunities. The enhanced performance is attributed to the increase in the thickness of the SiOx interfacial oxide layer.
In this paper, we investigate the effects of a SiOx interfacial layer on ON/OFF current ratios, endurance characteristics and read-disturb immunities of Ag/CuxO/SiOx/n+-Si write-once-read-many-times (WORM) memories. The CuxO active layers were prepared using a sol-gel process. After coating CuxO films on n+-Si substrates, the CuxO/n+-Si samples were annealed in air at 400 degrees C and 600 degrees C, respectively, to obtain a SiOx interfacial layer at the CuxO/n + -Si interfaces. The 400 degrees C-annealed CuxO device shows an ON/OFF current ratio of 104. However, degradation of OFF state current (IOFF) with increasing read-pulse cycles and stress time is observed. For the 600 degrees C-annealed CuxO device, stable ON and OFF state currents can be observed both in an endurance test for over 1.2 x 104 read cycles and in a read-disturb test for 2 x 104 s. Moreover, a higher ON/OFF current ratio of 107 is obtained. A rigorous retention test executed at an elevated temperature of 85 degrees C indicates that the data retention time is expected to last for 10 years. The performance improvement of the 600 degrees C-annealed CuxO device is due to an increase in the thickness of the SiOx interfacial oxide layer. The mechanism for the influence of the interfacial layer on memory performance is investigated and illustrated. The OFF state current of the memory is limited by hopping and trap-assisted tunneling transport in the SiOx interfacial layer. In the ON state, conductive paths in the device cause that the carriers can easily migrate by Ohmic and space charge limited conduction. (c) 2021 Elsevier B.V. All rights reserved.
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