Three-stage CMOS amplifier: Frequency compensated using fully differential block

The advancement of CMOS technology limits designers' options for multi-stage configurations as a promising alternative to cascade structures. The main issue of designing multi-stage amplifiers is frequency compensation since cascade structures are volatile. An efficient three-stage amplifier, which is frequency compensated using a fully differential block, is proposed in this work. The differential block enhances the Miller effect to reduce the size of compensation capacitors, and this leads to less die occupation. The compensation network shares the differential block between two Miller loops while two Miller capacitors at the outputs of the differential block cause pole-zero cancelation to increase operating frequency range. The proposed structure is modeled by a linear transfer function and simulated via HSPICE software using 0.18 mu m CMOS library. Simulation results indicate excellent performance and acceptable robustness against parameter mismatches and probable fabrication errors. According to the simulations, the proposed amplifier has a DC gain of 105dB, a gain-bandwidth product of 4.8MHz, a phase margin of 72 degrees, and a power dissipation of 360 mu. The high performance of the proposed three-stage amplifier with an enhanced figure of merit makes it a perfect alternative to the amplifiers based on the conventional reverse nested Miller compensation.

Automated summary

This paper proposes an efficient three-stage amplifier with frequency compensation using a fully differential block. By enhancing the Miller effect, the size of compensation capacitors is reduced, and the differential block is shared to increase the operating frequency range. Simulation results demonstrate excellent performance and acceptable robustness against parameter mismatches and fabrication errors.