Thermal design optimization of electronic circuit board layout with transient heating chips by using Bayesian optimization and thermal network model

This paper describes a method combining Bayesian optimization (BO) and a lumped-capacitance thermal network model that is effective for speeding up the thermal design optimization of an electronic circuit board layout with transient heating chips. As electronic devices have become smaller and more complex, the importance of thermal design optimization to ensure heat dissipation performance has increased. However, such a thermal design optimization is difficult because various trade-offs associated with packaging and transient temperature changes of heat-generating components must be considered. This study aims to improve the performance of thermal design optimization by artificial intelligence. BO using a Gaussian process was combined with the lumped-capacitance thermal network model, and its performance was verified. As a result, BO successfully found the ideal circuit board layout as well as particle swarm optimization (PSO) and genetic algorithm (GA) could. The CPU time for BO was 1/5 and 1/4 of that for PSO and GA. In addition, BO found a non-intuitive optimal solution in approximately 7 min from 10 million layout patterns. It was estimated that this was 1/10 0 0 of the CPU time required for analyzing all layout patterns. (c) 2021 The Authors. Published by Elsevier Ltd. This is an open access article under the CC BY license ( http://creativecommons.org/licenses/by/4.0/ )

Automated summary

This paper presents a method that combines Bayesian optimization and a lumped-capacitance thermal network model to accelerate the thermal design optimization of electronic circuit board layouts. The method successfully finds the ideal layout while significantly reducing the computational time.