4.3 Article

A new low-power Dynamic-GDI full adder in CNFET technology

Journal

INTEGRATION-THE VLSI JOURNAL
Volume 83, Issue -, Pages 46-59

Publisher

ELSEVIER
DOI: 10.1016/j.vlsi.2021.12.001

Keywords

Low-power; Full-adder; GDI; Dynamic logic; CNFET

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This paper proposes a new low-power full-adder circuit based on the proper combination of dynamic logic style and GDI low-power technique in CNFET technology. The proposed circuit achieves full-swing, full-adder cell and shows significant improvement in major circuit performances through simulations.
In this paper, a new low-power full-adder circuit based on the proper combination of dynamic logic style and Gate Diffusion Input (GDI) low-power technique is proposed in Carbon Nanotube Field Effect Transistor (CNFET) technology. Using the proposed approach, the basic logic circuits such as XOR and XNOR gates are implemented which results in a full-swing, full-adder cell in the CNFET technology. The proposed circuit is simulated in HSPICE using CNFET model parameters. Finally, the simulation results justify a good improvement in the major circuit performances such as power consumption, delay and power-delay product (PDP) parameters for the proposed full-adder circuit.

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