Journal
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume 30, Issue 5, Pages 666-670Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TVLSI.2022.3151479
Keywords
Pipelines; Calibration; Capacitors; Topology; Gain; Linearity; Clocks; Adaptive gain tuning; foreground calibration; mixed signal; multiplying digital-to-analog converter (MDAC) gain; pipelined analog-to-digital converter (ADC)
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This paper introduces a low-power mixed-signal foreground calibration algorithm for ADC using a digitally controlled reconfigurable switched-capacitor MDAC gain controller. The proposed method nullifies the effect of MDAC gain change on ADC output linearity through a feedback mechanism, achieving ideal ADC output linearity.
This manuscript introduces a low-power mixed-signal foreground calibration algorithm of a pipeline analog-to-digital converter (ADC) using a digitally controlled reconfigurable switched-capacitor multiplying digital-to-analog converter (MDAC) gain controller. The proposed calibration technique forces the front-end stage MDAC gain toward its ideal value to achieve the ideal ADC output linearity. In this brief, a feedback mechanism has been employed to nullify the effect of change in MDAC gain from its ideal value by sensing a digital back-end unit response. The proposed method has been simulated using a 0.18-mu m CMOS process. An 11-bit pipeline ADC with a 1.5-bit stage followed by a ten bit linear back-end ADC (BE-ADC) has been used to calibrate the non-linearity of the said 1.5-bit stage. Using a low amplifier gain value of 28 dB, the signal-to-noise-and-distortion ratio (SNDR) of the ADC improves from 46.21-dB pre-calibration to 65.13-dB post-calibration.
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