Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume 69, Issue 3, Pages 859-863Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSII.2021.3121245
Keywords
Analog-to-digital converter (ADC); successive approximation register (SAR); noise shaping; error feedback; unity-gain buffer
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Funding
- National Natural Science Foundation of China [62074119, 62090040, U19A2053, 62022065]
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This brief introduces a compact and energy efficient noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC) based on the error-feedback (EF) structure. The proposed architecture utilizes unity-gain buffer and delay elements operated in a ping-pong manner to perform EF function, resulting in high efficiency in achieving strong noise-shaping (NS) effect. The prototype NS-SAR ADC achieves impressive performance with low power consumption.
This brief presents a compact and energy efficient noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC) based on the error-feedback (EF) structure. Different from most prior works adopting the cascaded integrator feed-forward (CIFF) structure, the proposed architecture employs unity-gain buffer and delay elements operated in a ping-pong manner to perform EF function. Since to the lossless residue extraction and summation, it exhibits high efficiency in realizing the strong noise-shaping (NS) effect. Fabricated in a 65-nm 1P9M CMOS technology, the prototype NS-SAR ADC consumes 113.02 mu W when operating at a 1.2-V supply voltage and at a sampling rate of 20 MS/s. It achieves a peak Schreier FoM of 176.73 dB with a signal to noise and distortion-ratio (SNDR) of 79.3 dB at an oversampling ratio (OSR) of 16.
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