Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume 69, Issue 6, Pages 2423-2434Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2022.3151920
Keywords
Digital; logic; memristor; multilevel; RRAM; ternary
Categories
Funding
- National Natural Science Foundation of China [61871429]
- Natural Science Foundation of Zhejiang Province [LY18F010012]
- Australian Research Council (ARC) [LP150100693]
- Varian Semiconductor Equipment/Applied Materials through an ARC Linkage Project [LP150100693]
- Forrest Research Foundation
- Australian Research Council [LP150100693] Funding Source: Australian Research Council
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This paper presents a design of multi-stage hybrid memristor-CMOS ternary combinational logic stages that are optimized for reducing silicon area occupation. Experimental results show an improvement in data density of each logic block by a factor of 5.2x to 17.3x.
This paper presents a series of multi-stage hybrid memristor-CMOS ternary combinational logic stages that are optimized for reducing silicon area occupation. Prior demonstrations of memristive logic are typically constrained to single-stage logic due to the variety of challenges that affect device performance. Noise accumulation across subsequent stages can be amortized by integrating ternary logic gates, thus enabling higher density data transmission, where more complex computation can take place within a smaller number of stages when compared to single-bit computation. We present the design of a ternary half adder, a ternary full adder, a ternary multiplier, and a ternary magnitude comparator. These designs are simulated in SPICE using the broadly accessible Knowm memristor model, and we perform experimental validation of individual stages using an in-house fabricated Si-doped HfOx memristor which exhibits low cycle-to-cycle variation, and thus contributes to robust long-term performance. We ultimately show an improvement in data density in each logic block of between 5.2 x -17.3x, which also accounts for intermediate voltage buffering to alleviate the memristive loading problem.
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