Journal
IEEE ELECTRON DEVICE LETTERS
Volume 43, Issue 6, Pages 854-857Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2022.3171597
Keywords
Logic gates; Silicon; FeFETs; Nanoscale devices; Switches; Temperature measurement; MOSFET; Ferroelectrics; ferroelectric field effect transistor (FeFET); gate-all-around MOSFET; hafnium zirconium oxide; InAs; vertical nanowire
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Funding
- Swedish Research Council [2016-06186]
- European Research Council [101019147]
- Swedish Research Council [2016-06186] Funding Source: Swedish Research Council
- European Research Council (ERC) [101019147] Funding Source: European Research Council (ERC)
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The study demonstrates a successful process scheme for integrating a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon, showing promising device characteristics but limited by access resistance.
We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs.
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