Synapse and Tunable Leaky-Integrate Neuron Functions Enabled by Oxide Trapping Dynamics in a Single Logic Transistor

We show that a high-k gated n-MOSFET can embody both the memory plasticity of a synapse and leaky-integration of a neuron, by virtue of the rich temporal dynamics of charge capture/emission by gate-oxide defects. In addition, a tunable leaky-integrate function is demonstrated. The lower limit of energy per input spike is on the order of fJ, which provides room for low-power trigger circuit design and scalability. This work points to the prospect of a gate-engineered logic transistor serving as the universal building block of hardware spiking neural networks, thereby accelerating the realization of compact, energy efficient neuromorphic computers given the relative maturity of the transistor technology.

Automated summary

High-k gated n-MOSFET can exhibit the memory plasticity of a synapse and the leaky-integration of a neuron through the temporal dynamics of charge capture/emission by gate-oxide defects. It also demonstrates a tunable leaky-integrate function. The research opens up possibilities for low-power trigger circuit design and scalability.