High Energy Efficiency and Linearity Switching Scheme Without Reset Energy for SAR ADC

A high energy efficiency and linearity switching scheme is proposed for the successive approximation register (SAR) analog-to-digital converter (ADC). With the tri-level switching scheme, the capacitor area is reduced by 75% compared with the conventional switching scheme. In addition, the proposed switching scheme also combines the most significant bit (MSB) splitting method and the monotonic switching scheme for linearity and energy efficiency improvement. Furthermore, by inserting a connection switch between the MSB splitting capacitors and the least significant bit (LSB) capacitors, the reset energy can be avoided. The MATLAB simulation results show that compared to the monotonic switching scheme, the proposed switching scheme achieves a 93.29% reduction in average switching energy and 50% capacitor area saving without the reset energy when the parasitic capacitance is taken into consideration. Meanwhile, the linearity is enhanced by root 2 x from the Monte Carlo simulation. The post-simulation results indicate that a 10-bit SAR ADC with the proposed switching scheme can achieve a signal-to-noise distortion ratio (SNDR) of 57.81 dB and a spurious-free dynamic range (SFDR) of 68.63 dB at the sampling rate of 1 MS/s in a 180-nm CMOS process. The SAR ADC consumes 15.25 mu W power at a 1 V supply, resulting in a figure of merit (FoM) of 24.03 fJ/conv.-step. The active area of this ADC is only 0.057 mm(2).

Automated summary

A high energy efficiency and linearity switching scheme is proposed for the SAR ADC. The proposed scheme reduces the capacitor area by 75% compared to the conventional scheme and improves linearity and energy efficiency using the MSB splitting method and monotonic switching scheme. The simulation results demonstrate significant reductions in switching energy and capacitor area, as well as enhanced linearity.