Design of a low power and robust VLSI power line interference canceler with optimized arithmetic operators

The electric generator's functional performance suffers from harmonic distortions such as first, second, and third-order. This work proposes a low power dissipation VLSI hardware architecture for a robust power line interference canceling (PLIC) in biopotential signals. Our proposed Least Mean Square (LMS) architecture presents just four clock cycles of latency per sample. The Harmonic Generator (HG) architectures are exploited and optimized in their arithmetic operations. We substituted conventional multipliers with adders and shifters and used efficient and previously published squarer units. In particular, the combination of radix-4 squarer unit and 3-2 subtractor compressor architecture is an efficient alternative for use in the HG. Our VLSI synthesis results show that combining the optimized adaptive filters LMS and HG's hardware architecture, the proposed approach turns the PLIC VLSI structure robust and power-efficient. It effectively suppresses interferences in ECG (Electrocardiogram), EEG (Electroencephalogram), EMG (Electromyogram), and EOG (Electrooculogram) signals. Notably, the PLIC architecture is more efficient in the circuit area and power dissipation with the radix-4 and 3-2 subtractor compressor in the HG, saving up to 4.98 times in total power and 30.46% in the VLSI area, compared to the state-of-the-art solution.

Automated summary

This study proposes a low power dissipation VLSI hardware architecture for interference canceling in biopotential signals. By utilizing optimized hardware architectures and efficient arithmetic operations, the proposed approach achieves low latency and power-efficient performance. The experimental results demonstrate its effectiveness in suppressing interferences in various biopotential signals, and its superiority in terms of circuit area and power dissipation compared to existing solutions.