Compact Modeling Technology for the Simulation of Integrated Circuits Based on Graphene Field-Effect Transistors

The progress made toward the definition of a modular compact modeling technology for graphene field-effect transistors (GFETs) that enables the electrical analysis of arbitrary GFET-based integrated circuits is reported. A set of primary models embracing the main physical principles defines the ideal GFET response under DC, transient (time domain), AC (frequency domain), and noise (frequency domain) analysis. Another set of secondary models accounts for the GFET non-idealities, such as extrinsic-, short-channel-, trapping/detrapping-, self-heating-, and non-quasi static-effects, which can have a significant impact under static and/or dynamic operation. At both device and circuit levels, significant consistency is demonstrated between the simulation output and experimental data for relevant operating conditions. Additionally, a perspective of the challenges during the scale up of the GFET modeling technology toward higher technology readiness levels while drawing a collaborative scenario among fabrication technology groups, modeling groups, and circuit designers, is provided.

Automated summary

This article reports the progress made towards the development of a modular compact modeling technology for graphene field-effect transistors (GFETs) that allows for the electrical analysis of GFET-based integrated circuits. It presents a set of primary and secondary models to capture both the ideal and non-ideal response of GFETs, and demonstrates consistency between simulation and experimental data. Furthermore, it discusses the challenges and collaboration opportunities in scaling up the GFET modeling technology towards higher technology readiness levels.