Journal
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS
Volume 18, Issue 4, Pages -Publisher
ASSOC COMPUTING MACHINERY
DOI: 10.1145/3524061
Keywords
CNFET; full adder; image processing; motion detection; edge detection
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This paper presents a novel and efficient inexact Full Adder cell utilizing carbon nanotube field-effect transistor (CNFET) technology and two logic styles - conventional CMOS (C-COMS) and pass transistor logic (PTL). Extensive simulations at transistor level and application level demonstrate higher performance in terms of power-delay-area product (PDAP compared to latest designs. Application level simulations using MATLAB show the quality of output images in terms of peak signal-to-noise ratio (PSNR) and structural similarity (SSIM). The proposed circuit shows significant improvement in power-delay-area-PSNR product (PDAPP) and power-delay-area-SSIM product (PDASP) compared to its counterparts.
In this paper, a novel and highly efficient inexact Full Adder cell by exploiting two logic styles including conventional CMOS (C-COMS) and pass transistor logic (PTL) are presented. The so-called carbon nanotube field-effect transistor (CNFET) technology is used to implement circuits at the transistor level. To justify the efficiency of our design, extensive simulations are performed at the transistor level as well as application level. Transistor-level simulations which are carried out by the HSPICE 2008 tool, demonstrate at least 12% higher performance in terms of power-delay-area product (PDAP) of the proposed circuit compared to the latest designs. At the application level, by using the MATLAB tool, inexact Full Adders are employed in the structure of the ripple carry adder (RCA) that is applied in motion and edge detection algorithms. Computer simulation results confirm the appropriate quality of the output images in terms of the peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) criteria. At last, to make a compromise between hardware and application level parameters, the power-delay-area-1/PSNR product (PDAPP) and power-delay-area-1/SSIM product (PDASP) are considered as figures of merit. The proposed circuit shows remarkable improvement from the PDAPP and PDASP points of view compared to its counterparts.
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