Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC

A 2-then-1-bit/cycle noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC) for high sampling rate and high resolution is presented. The conversion consists of two phases of a coarse 2-bit/cycle SAR conversion for high speed and a fine 1-bit/cycle noise-shaping SAR conversion for high accuracy. The coarse conversion is performed by both voltage and time comparison for low power consumption. A redundancy after the coarse conversion corrects the error caused by a jitter noise during the time comparison. Additionally, a mismatch error between signal and reference paths is eliminated with the help of a tail-current-sharing comparator. The proposed ADC was designed in a 28 nm CMOS process, and the simulation result shows a 68.2 dB signal-to-noise distortion (SNDR) for a sampling rate of 480 MS/s and a bandwidth of 60 MHz with good energy efficiency.

Automated summary

The SAR ADC presented in this study utilizes a 2-then-1-bit/cycle noise-shaping architecture to achieve high sampling rate and high resolution. It combines coarse and fine conversion phases to achieve both speed and accuracy, while implementing techniques to reduce power consumption, correct errors, and eliminate mismatch between paths. The ADC was designed in a 28 nm CMOS process and demonstrated good energy efficiency with a SNDR of 68.2 dB at a sampling rate of 480 MS/s and a bandwidth of 60 MHz.