Highly-Parallel FPGA Accelerator for Simulated Quantum Annealing

Quantum annealing (QA) is a method to find the global optimum of a combinatorial optimization problem by using quantum fluctuations. Quantum annealers such as D-wave are efficient to solve small problems with less than 2048 variables. Simulated quantum annealing on digital computers allows us to solve large real-world problems. However, the processing time increases exponentially with the number of variables. This article proposes a highly-parallel accelerator for simulated quantum annealing exploiting spatial and temporal parallelism. The accelerator is implemented using open computing language (OpenCL) on FPGA. For 8,192 spin models, we achieve 145 times speed using 32 Trotters in one FPGA and 290 times speed-up using 64 Trotters in two FPGAs, compared to single-core CPU implementation.

Automated summary

Quantum annealing is a method to solve combinatorial optimization problems by utilizing quantum fluctuations, but the processing time increases exponentially with the number of variables. This article introduces a highly-parallel accelerator implemented on FPGA, which achieves significant speed-up compared to single-core CPU implementation.