A Survey of Domain-Specific Architectures for Reinforcement Learning

Reinforcement learning algorithms have been very successful at solving sequential decision-making problems in many different problem domains. However, their training is often time-consuming, with training times ranging from multiple hours to weeks. The development of domain-specific architectures for reinforcement learning promises faster computation times, decreased experiment turn-around time, and improved energy efficiency. This paper presents a review of hardware architectures for the acceleration of reinforcement learning algorithms. FPGA-based implementations are the focus of this work, but GPU-based approaches are considered as well. Both tabular and deep reinforcement learning algorithms are included in this survey. The techniques employed in different implementations are highlighted and compared. Finally, possible areas for future work are suggested, based on the preceding discussion of existing architectures.

Automated summary

This paper presents a review of hardware architectures for accelerating reinforcement learning algorithms, focusing on FPGA-based implementations and considering GPU-based approaches as well. It compares the techniques employed in different implementations and suggests possible areas for future work.