Perhydropolysilazane Charge-Trap Layer in Solution-Processed Organic and Oxide Memory Thin-Film Transistors

The charge trapping property of spin-coated perhydropolysilazane (PHPS) layers for solution-processed organic and oxide thin film memory transistors is demonstrated. The nitrogen content within the PHPS layer is decreased by increasing the annealing temperatures from room temperature to 450 degrees C. The PHPS layer added to the SiO2 gate insulator in the charge trap memories (CTMs) shows good memory functionalities which are electrically programmable, and is erased either electrically or optically depending on the semiconductor used. The stored or erased charges in the p-type semiconductor-based CTM result in relatively large threshold voltage shifts ( increment V-TH > 60 V) and large memory on- and off-current ratio (I-M,I-ON/I-M,I-OFF > 10(3)) with the respective memory output current extrapolated to 10(8) s. The n-type CTM shows increment V-TH approximate to 20 V, I-M,I-ON/I-M,I-OFF of 0.5 x 10(3) and is extrapolated to 10(15) s. It is concluded that the origin of the charge-traps in both the p-type and n-type CTMs mainly originates from the PHPS charge trap layer (CTL) and greatly occurs in highly concentrated nitrogen PHPS layers. There is a high possibility of using the PHPS CTL in a wide variety of cost-effective CTMs even with high temperature processed semiconductors.

Automated summary

The charge trapping property of spin-coated perhydropolysilazane (PHPS) layers for solution-processed organic and oxide thin film memory transistors is demonstrated. The PHPS layer shows good memory functionalities in charge trap memories (CTMs) and can be programmed and erased electrically or optically.