4.7 Article

An Organic/Inorganic Nanomaterial and Nanocrystal Quantum Dots-Based Multi-Level Resistive Memory Device

Journal

NANOMATERIALS
Volume 11, Issue 11, Pages -

Publisher

MDPI
DOI: 10.3390/nano11113004

Keywords

CdSe/ZnS quantum dots; multi-level memory; PEDOT:PSS; ZnO nanoparticles

Funding

  1. Korea Innovation Foundation (INNOPOLIS) - Korea government (MSIT) [2020-DD-UP-0348]
  2. Korea Institute of Industrial Technology

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A multi-level memory device based on cadmium selenide/zinc sulfide quantum dots was developed, utilizing two layers of QD thin films as charge storage layers to achieve three states. Zinc oxide and aluminum oxide were incorporated to prevent leakage, with optimized fabrication conditions for each thin film.
A cadmium selenide/zinc sulfide (CdSe/ZnS) quantum dot (QD)-based multi-level memory device with the structure [ITO/PEDOT:PSS/QDs/ZnO/Al:Al2O3/QDs/Al] was fabricated via a spin-coating method used to deposit thin films. Two layers of QD thin films present in the device act as charge storage layers to form three distinct states. Zinc oxide (ZnO) and aluminum oxide (Al2O3) were added to prevent leakage. ZnO NPs provide orthogonality between the two QD layers, and a poly(3,4-ethylenedioxythio-phene): poly(styrenesulfonate) (PEDOT:PSS) thin film was formed for effective hole injection from the electrodes. The core/shell structure of the QDs provides the quantum well, which causes the trapping of injected charges. The resistance changes according to the charging and discharging of the QDs' trap site and, as a result, the current through the device also changes. There are two quantum wells, two current changes, and three stable states. The role of each thin film was confirmed through I-V curve analysis and the fabrication conditions of each thin film were optimized. The synthesized QDs and ZnO nanoparticles were evaluated via X-ray diffraction, transmission electron microscopy, and absorbance and photoluminescence spectroscopy. The measured write voltages of the fabricated device were at 1.8 and 2.4 V, and the erase voltages were -4.05 and -4.6 V. The on/off ratio at 0.5 V was 2.2 x 10(3). The proposed memory device showed retention characteristics of & GE;100 h and maintained the initial write/erase voltage even after 200 iterative operations.

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