4.6 Article

Macro-Modeling for N-Type Feedback Field-Effect Transistor for Circuit Simulation

Journal

MICROMACHINES
Volume 12, Issue 10, Pages -

Publisher

MDPI
DOI: 10.3390/mi12101174

Keywords

feedback field-effect transistor; macro-model; compact modeling; hybrid inverter; spike neural network

Funding

  1. Basic Science Research Program through NRF of Korea - Ministry of Education [NRF-2019R1A2C1085295]

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This study introduces an improved macro-model for an N-type feedback field-effect transistor (NFBFET) and verifies its effectiveness through comparison with a previous model and circuit simulation. The new model consists of two parts, a charge integrator circuit and a current generator circuit, addressing previous issues in accurately implementing certain characteristics.
In this study, we propose an improved macro-model of an N-type feedback field-effect transistor (NFBFET) and compare it with a previous macro-model for circuit simulation. The macro-model of the NFBFET is configured into two parts. One is a charge integrator circuit and the other is a current generator circuit. The charge integrator circuit consisted of one N-type metal-oxide-semiconductor field-effect transistor (NMOSFET), one capacitor, and one resistor. This circuit implements the charging characteristics of NFBFET, which occur in the channel region. For the previous model, the current generator circuit consisted of one ideal switch and one resistor. The previous current generator circuit could implement I-DS-V-GS characteristics but could not accurately implement I-DS-V-DS characteristics. To solve this problem, we connected a physics-based diode model with an ideal switch in series to the current generator circuit. The parameters of the NMOSFET and diode used in this proposed model were fitted from TCAD data of the NFBFET, divided into two parts. The proposed model implements not only the I-DS-V-GS characteristics but also the I-DS-V-DS characteristics. A hybrid inverter and an integrate and fire (I & F) circuit for a spiking neural network, which consisted of NMOSFETs and an NFBFET, were simulated using the circuit simulator to verify a validation of the proposed NFBFET macro-model.

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