Wafer-Level 3D Integration Based on Poly (Diallyl Phthalate) Adhesive Bonding

Three-dimensional integration technology provides a promising total solution that can be used to achieve system-level integration with high function density and low cost. In this study, a wafer-level 3D integration technology using PDAP as an intermediate bonding polymer was applied effectively for integration with an SOI wafer and dummy a CMOS wafer. The influences of the procedure parameters on the adhesive bonding effects were determined by Si-Glass adhesive bonding tests. It was found that the bonding pressure, pre-curing conditions, spin coating conditions, and cleanliness have a significant influence on the bonding results. The optimal procedure parameters for PDAP adhesive bonding were obtained through analysis and comparison. The 3D integration tests were conducted according to these optimal parameters. In the tests, process optimization was focused on Si handle-layer etching, PDAP layer etching, and Au pillar electroplating. After that, the optimal process conditions for the 3D integration process were achieved. The 3D integration applications of the micro-bolometer array and the micro-bridge resistor array were presented. It was confirmed that 3D integration based on PDAP adhesive bonding is suitable for the fabrication of system-on-chip when using MEMS and IC integration and that it is especially useful for the fabrication of low-cost suspended-microstructure on-CMOS-chip systems.

Automated summary

Three-dimensional integration technology using PDAP as an intermediate bonding polymer was effectively applied in this study for wafer-level integration. The influences of procedure parameters on the adhesive bonding effects were determined through Si-Glass adhesive bonding tests, leading to the identification and optimization of optimal process conditions for 3D integration. This technology was found to be suitable for system-on-chip fabrication, especially for low-cost suspended-microstructure on-CMOS-chip systems.