Dual-Wavelength Time-Resolved Photoluminescence Study of CdSe$_\text{x}$Te$_\text{1-x}$ Surface Passivation via Mg$_\text{y}$Zn$_\text{1-y}$O and Al$_\text{2}$O$_\text{3}$

Voltage loss is currently one of the biggest challenges facing cadmium telluride (CdTe) based photovoltaics. Determining the location(s) of major voltage loss within the device stack (e.g., front/back interface, grain boundaries) is therefore of primary interest. Here, we present a custom-built time-resolved photoluminescence system with two excitation wavelengths-670 (standard) and 405 nm-to probe the device stack at depths of approximately 130 and 35 nm, respectively; their comparison helps differentiate interface and bulk contributions to carrier lifetime. We apply this system to examine the passivation effect of two significant recent advances in CdTe: the incorporation of Se to form graded CdSe$_\text{x}$Te$_\text{1-x}$ and the replacement of CdS with Mg$_\text{y}$Zn$_\text{1-y}$O. It is found that x = 0.2 Se is required to obtain lifetime improvements, primarily in the bulk. Additionally, evidence for trapping at the Mg$_\text{y}$Zn$_\text{1-y}$O/CdSe$_\text{x}$Te$_\text{1-x}$ interface was observed. This indicates further work is required to sufficiently passivate the front interface.

Automated summary

Determining major voltage losses in CdTe-based photovoltaics is crucial, with this study finding that a Se ratio of x = 0.2 is necessary for improving carrier lifetime in the bulk. The investigation also revealed evidence of trapping at the Mg$_\text{y}$Zn$_\text{1-y}$O/CdSe$_\text{x}$Te$_\text{1-x}$ interface, indicating further work is needed for proper passivation.