4.7 Article

Analysis and design of diode physical limit bandwidth efficient rectification circuit for maximum flat efficiency, wide impedance, and efficiency bandwidths

Journal

SCIENTIFIC REPORTS
Volume 11, Issue 1, Pages -

Publisher

NATURE PORTFOLIO
DOI: 10.1038/s41598-021-99405-7

Keywords

-

Funding

  1. JSPS KAKENHI [21K04178]
  2. MIC/SCOPE [21452069]
  3. Foundation for Technology Promotion for Electronic Circuit Board
  4. Murata Science Foundation
  5. VDEC
  6. University of Tokyo
  7. Keysight Technologies Japan, Ltd.
  8. Grants-in-Aid for Scientific Research [21K04178] Funding Source: KAKEN

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This paper proposes a novel rectification circuit for wideband voltage doubler rectifiers, which achieves efficient rectification with minimal inter-stage matching that includes a short-circuit stub and a virtual battery, overcoming existing problems in RF-dc conversion efficiency bandwidths.
Generally, a conventional voltage doubler circuit possesses a large variation of its input impedance over the bandwidth, which results in limited bandwidth and low RF-dc conversion efficiency. A basic aspect for designing wideband voltage doubler rectifiers is the use of complex matching circuits to achieve decade and octave impedance and RF-dc conversion efficiency bandwidths. Still, the reported techniques till now have been accompanied by a large fluctuation of the RF-dc conversion efficiency over the operating bandwidth. In this paper, we propose a novel rectification circuit with minimal inter-stage matching that consists of a single short-circuit stub and a virtual battery, which contributes negligible losses and overcomes these existing problems. Consequently, the proposed rectifier circuit achieves a diode physical-limit-bandwidth efficient rectification. In other words, the rectification bandwidth, as well as the peak efficiency, are controlled by the length of the stub and the physical limitation of the diodes.

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