4.5 Article

Timing Jitter Analysis and Mitigation in Hybrid OFDM-DFMA PONs

Journal

IEEE PHOTONICS JOURNAL
Volume 13, Issue 6, Pages -

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JPHOT.2021.3121168

Keywords

5G; analogue-digital conversion; digital-analogue conversion; digital filter multiple access; digital signal processing (DSP); orthogonal frequency division multiplexing (OFDM); passive optical networks (PONs); timing jitter

Funding

  1. DSP Centre of Excellence - European Regional Development Fund (ERDF) through the Welsh Government

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Hybrid OFDM-DFMA PONs provide a cost-effective solution for next-generation optical and 5G networks. This paper investigates the impact of DAC/ADC timing jitter on performance and introduces a DSP-based technique to mitigate the effects and reduce optical power penalties, ultimately reducing implementation costs.
Hybrid orthogonal frequency division multiplexing-digital filter multiple access passive optical networks (OFDMDFMA PONs) offer a cost-effective solution to the challenging requirements of next-generation optical access networks and 5G and beyond radio access networks. It is crucial to consider the impact of timing jitter in any ADC/DAC-based system, therefore this paper presents an in-depth investigation into the impacts of DAC/ADC timing jitter on the hybrid OFDM-DFMA PON's performance. We introduce improved accuracy white and coloured, DAC and ADC timing jitter models, applicable to any DSP- based transmission system. We prove that DAC and ADC timing jitter effects are virtually identical and investigate the effects of white/coloured timing jitter on upstream performance in hybrid OFDM-DFMA PONs and determine the associated jitter-induced optical power penalties. To mitigate against the timing jitter-induced performance degradations, a simple, but highly effective DSP-based technique is implemented which increases robustness against the timing jitter effects and significantly reduces timing jitter-induced optical power penalties. This consequently relaxes DAC/ADC sampling clock jitter requirements and so reduces implementation costs. White (coloured) timing jitter effects are shown to be independent of (dependent on) ONU operating frequency band and a trade-off between DAC and ADC jitter levels can be exploited to reduce ONU costs.

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