Journal
NATURE NANOTECHNOLOGY
Volume 17, Issue 3, Pages 278-+Publisher
NATURE PORTFOLIO
DOI: 10.1038/s41565-021-01034-8
Keywords
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Funding
- Air Force Office of Scientific Research under the MURI-FATE program [FA9550-15-1-0514]
- NSFC [51672005]
- Natural Science Foundation of Beijing [2212028]
- US Army Research Office through the Institute for Soldier Nanotechnologies [W911NF-18-2-0048]
- US Army Research Office [W911NF-18-1-0431]
- STC Center for Integrated Quantum Materials, NSF [DMR-1231319]
- Center for Energy Efficient Electronics Science (NSF) [0939514]
- Office of Naval Research [N00014-19-1-2296]
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In this study, a non-destructive soft-lock drawing method was developed to assemble high-density horizontal arrays of single-walled carbon nanotubes (CNTs). The assembled CNT bundles were then used as nanometer electrical contacts in high-density monolayer molybdenum disulfide (MoS2) transistors, demonstrating their potential for future electronic devices and advanced integration technologies.
The assembly of single-walled carbon nanotubes (CNTs) into high-density horizontal arrays is strongly desired for practical applications, but challenges remain despite myriads of research efforts. Herein, we developed a non-destructive soft-lock drawing method to achieve ultraclean single-walled CNT arrays with a very high degree of alignment (angle standard deviation of similar to 0.03 degrees). These arrays contained a large portion of nanometre-sized CNT bundles, yielding a high packing density (similar to 400 mu m(-1)) and high current carrying capacity (similar to 1.8 x 10(8) A cm(-2)). This alignment strategy can be generally extended to diverse substrates or sources of raw single-walled CNTs. Significantly, the assembled CNT bundles were used as nanometre electrical contacts of high-density monolayer molybdenum disulfide (MoS2) transistors, exhibiting high current density (similar to 38 mu A mu m(-1)), low contact resistance (similar to 1.6 k Omega mu m), excellent device-to-device uniformity and highly reduced device areas (0.06 mu m(2) per device), demonstrating their potential for future electronic devices and advanced integration technologies.
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