4.3 Article

Large array device characteristics improvements

Journal

MICROELECTRONICS RELIABILITY
Volume 125, Issue -, Pages -

Publisher

PERGAMON-ELSEVIER SCIENCE LTD
DOI: 10.1016/j.microrel.2021.114353

Keywords

Large array device (LAD); Electrostatic discharge (ESD); Resistor to protect gate oxide (RPO); N-type metal oxide semiconductor transistor; (NMOST); Human body mode (HBM); Machine mode (MM); Electrical safe operation area (eSOA); Signal control switching (SCS); Transmission line pulse generator (TLPG); Thermal or 2nd breakdown voltage; current; (Vt2; It2)

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A novel signal control switching architecture is proposed in this paper to enhance the ESD performance of large array devices, with only a small increase in layout area, significant improvement in electrostatic discharge robustness and electrical safe operation area characteristics can be achieved. This study is conducted in 0.15 μm Bipolar CMOS DMOS (BCD) with silicide technologies.
Large array devices are often used for big current driving capabilities in power electronic integrated circuit (IC) applications. Since these structures have big sizes, typical electrostatic discharge protection methodologies cannot be applied in such kind of IC. Otherwise, IC will become too huge to marketing. In this paper, a novel signal control switching architecture for adding large array devices' ESD performances is proposed. Only a little layout area is increased, but a huge electrostatic discharge robustness improvement can be obtained. Moreover, electrical safe operation area characteristics of large array devices are also improved very much with this new scheme. This study is processed in 0.15 mu m Bipolar CMOS DMOS (BCD) with silicide technologies.

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