Journal
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume 24, Issue 3, Pages 954-967Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TVLSI.2015.2420954
Keywords
Lifetime; nonvolatile cache (NV-cache); wear-leveling; write endurance
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Emerging nonvolatile memory technologies, such as spin-transfer torque RAM or resistive RAM, can increase the capacity of the last-level cache (LLC) in a latency and power-efficient manner. These technologies endure 10(9)-10(12) writes per cell, making a nonvolatile cache (NV-cache) with a lifetime of dozens of years under ideal working conditions. However, nonuniformity in writes to different cache lines considerably reduces the NV-cache lifetime to a few months. Writes to cache lines can be made uniformly by wear-leveling. A suitable wear-leveling for NV-cache should not incur high storage and performance overheads. We propose a novel, simple, and effective wear-leveling technique with negligible performance overhead of <0.4% for memory-intensive workloads. Our proposal consists of two mechanisms: 1) a wear-leveling mechanism within each cache set that slightly increases main memory write-back traffic and LLC miss rate and 2) a novel technique to reduce cache interset variation which causes minimum interference with normal cache operation. Using these mechanisms, we show that the lifetime of the NV-cache is boosted up to 13x for different cache configurations.
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