Journal
IEEE TRANSACTIONS ON POWER ELECTRONICS
Volume 31, Issue 12, Pages 8042-8045Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TPEL.2016.2562030
Keywords
DBC layout; parallel connection; SiC MOSFET; power module; packaging technology
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This letter proposes a novel direct bonded copper (DBC) layout for mitigating the current imbalance among the paralleled SiC MOSFET dies in multichip power modules. Compared to the traditional layout, the proposed DBC layout significantly reduces the circuit mismatch and current coupling effect, which consequently improves the current sharing among the paralleled SiC MOSFET dies in power module. Mathematic analysis and circuit model of the DBC layout are presented to elaborate the superior features of the proposed DBC layout. Simulation and experimental results further verify the theoretical analysis and current balancing performance of the proposed DBC layout.
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