A Smart Gate Driver IC for GaN Power HEMTs With Dynamic Ringing Suppression

Conventional di/dt and dv/dt control and gate protection techniques for gallium nitride (GaN) power transistors usually employ external controllers, isolation circuits, discrete pull-up, and pull-down resistors. With large number of components, power modules become more complex and may introduce additional parasitic. Gate driver ICs with segmented output stages and dynamic gate driving have been reported previously to be effective in simultaneously suppressing gate ringing and overshoot voltage while maintaining fast switching speed. However, the programming for dynamic gate driving is rather complicated, requiring the user to load a sequence of driving patterns obtained from trial and error ahead of time. This article presents a gate driver IC for E-mode GaN power transistors with seven segmented output stages. More importantly, it offers a simplified programming method for the dynamic gate driving pattern. The optimal gate drive pattern can be defined by simply adjusting one external bias resistor. The proposed method eliminates the complex trial and error digital control, and can potentially promoting the wider acceptance of dynamic gate driving by the industry. The timing resolution for the gate drive pattern can be varied in steps from 0.5 to 5 ns. It can also be used to drive many commercially available GaN power transistors.

Automated summary

Conventional gate protection techniques for GaN power transistors may introduce additional parasitic due to the large number of components, while dynamic gate driving, although effective, requires complicated programming. This article proposes a simplified method for dynamic gate driving, allowing the optimal gate drive pattern to be defined by adjusting one external bias resistor, reducing the need for trial and error and digital control.