Suppression of Chattering in the Real-Time Simulation of the Power Converter

The achievement of the time-step below 500-ns in the field-programmable-gate-arrays (FPGAs)-based real-time simulation is of importance for the power converters having high switching frequencies. However, most of the existing focus on addressing the power converter modeling under the continuous conduction mode (CCM). Nevertheless, toward practical applications, the modeling of discontinuous conduction mode (DCM) with a light-load is of a greater challenge due to the chattering around zero point. In order to solve the chattering problem under the light-load, this article proposes a zero-regulation (ZR) method for FPGA-based real-time simulation. The proposed ZR method can not only represent CCM and DCM with a unified formula but also solve the chattering problem and improve accuracy and stability. In addition, results using different switch models are also given to demonstrate the feasibility and the generality of the proposed method. Finally, a case study of the series load resonant converter is presented. Simulation results are validated against a reference model at a 100-ns time step and a 10-kHz switching frequency.

Automated summary

This article proposes a zero-regulation method for FPGA-based real-time simulation to address the chattering problem under light-load, achieving unified modeling of CCM and DCM, as well as improving accuracy and stability.