Journal
IEEE TRANSACTIONS ON NUCLEAR SCIENCE
Volume 69, Issue 2, Pages 169-180Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNS.2022.3143652
Keywords
Error correction codes; Error correction; Estimation; Very large scale integration; Protons; Probability; Physics; Error correction codes (ECCs); multiple bit upsets (MBUs); single event effects (SEEs); SRAM
Funding
- Spanish MINECO Projects [TIN2017-87237, PID2020-112916GB-I00]
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This article studies the reliability of state-of-the-art ECC techniques designed for memories to maintain data integrity under radiation or hazardous conditions. Easy-to-use equations are provided to estimate the probability of error occurrence in a memory implementing different ECCs.
Modern nanoscale devices with storage capacity typically implement error correction codes (ECCs) in order to cope with the effects of natural radiation. Thus, different state-of-the-art ECC techniques aim at preventing data corruption when different numbers of errors (or bitflips) occur in the same logical memory word. However, even though bit interleaving prevents a single particle (such as a proton or a neutron) from flipping several cells in the same word, it cannot be discarded that two independent events may affect nearby cells in the same word and, therefore, would provoke a multiple bit upset (MBU) or equivalent. This article studies the reliability of various state-of-the-art ECC techniques designed for memories to maintain their data integrity under radiation or any other hazardous conditions, where said event accumulation is likely to occur. For this purpose, a set of easy-to-use equations will be provided to estimate the probability of error occurrence in a memory that implements different ECCs, as a function of the number of accumulated bitflips, size of the memory, and word size.
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