Low Parasitic-Inductance Packaging of a 650 V/150 A Half-Bridge Module Using Enhancement-Mode Gallium-Nitride High Electron Mobility Transistors

Because of their fast-switching speed and small die size, gallium-nitride high electron mobility transistors are challenging to package for low parasitic inductance and high heat dissipation in power electronics applications. In this article, a packaging technique was developed for making half-bridge modules of a 650 V, 150 A enhancement-mode gallium-nitride power transistor. The package consists of the device chips interconnected between a printed circuit board and an aluminum-nitride direct-bonded copper substrate. The dice are bonded on the insulated ceramic substrate by silver-sintering to ensure high thermal performance and joint reliability. The source, drain, and gate pads are connected by silver-sintering gold-plated pins or silver rods, which are aligned by holes or grooves in the circuit board. For electrical insulation and mechanical robustness, the space surrounding the device is filled by injecting and curing an underfill polymer. Electrical and thermal simulations of the package show that the half-bridge module has a 1.122 nH power-loop inductance, and 0.099 degrees C/W junction-to-case thermal resistance. Packages of the half-bridge module were fabricated, and their static and dynamic performances were characterized.

Automated summary

A packaging technique for gallium-nitride power transistors was developed to address the challenges of low parasitic inductance and high heat dissipation.