LaSiOx- and Al2O3-Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration

Sequential 3-D stacking of multiple CMOS device tiers in a single fabrication flow requires the development of reliable high-k/metal gate (HKMG) stacks at a reduced thermal budget (<525 degrees C). The omission of the customary high-temperature gate-stack annealing results in excessive dielectric defect densities. We have recently demonstrated on MOS capacitors the insertion of defect decoupling layers-LaSiOx for nMOS and Al2O3 for pMOSat the interface between SiO2 and HfO2 as a promising approach to engineer the high- k band lineup and minimize charge trapping for improved bias-temperature-instability (BTI) reliability. In this article, we demonstrate this approach in planar transistors, which allows assessing the impact of defect decoupling on carrier mobility. First, a comparative study on the impact of LaSiOx and Al2O3 insertion is performed, highlighting the different strategies for improving positive BTI (PBTI) and negative BTI (NBTI) reliability. Second, a comprehensive investigationon the effects of LaSiOx and Al2O3 insertion is conducted with a focus on BTI reliability and channel carrier mobility: a lack of penalty (Al2O3) or even improved carrier mobility (LaSiOx) is reported for the dipole-inserted gate stacks. Furthermore, we explore the simplified dual gate-stack integration for CMOS flow. AseverePBTI reliabilitypenalty is observedif an Al2O3 layer (for hole trap decoupling) is deposited in the nMOS gatestack, even if on top of the beneficial LaSiOx (for electron trap decoupling). In contrast, the pMOS gate- stack is found to be more tolerant to the presence of a residual LaSiOx layer on top of the beneficial Al2O3 layer, suggesting a viable strategy for the simplified dual gate-stackintegration. Finally, the reliability improvement is validated also on a FinFET test vehicle.

Automated summary

This article proposes a method to improve the reliability of high-k/metal gate structures by inserting defect decoupling layers between SiO2 and HfO2. The study shows that LaSiOx has little impact on carrier mobility, while Al2O3 can improve both positive and negative BTI reliability. Furthermore, the simplified dual gate-stack integration strategy is explored, indicating that the pMOS gate-stack is more tolerant to the presence of a residual LaSiOx layer.